1. Field of the Invention
The present invention relates to a local oscillator circuit useful as part of a semiconductor integrated circuit, more particularly to frequency sensitivity compensation in the local oscillator.
2. Description of the Related Art
FIG. 14 shows a block diagram of a conventional local oscillator circuit comprising a phase detector 1, a charge pump 2, a loop filter 3, a voltage-controlled oscillator 4, a prescaler 5, a programmable counter 6, a logic circuit 7, and an analog-to-digital converter (ADC) 8. These circuit elements are connected to form a control loop that locks the output frequency (fout) of the voltage-controlled oscillator 4 at a programmable multiple of a reference frequency fs, as selected by data D output from the logic circuit 7 to the programmable counter 6. All of these circuit elements may be integrated into a semiconductor substrate.
FIG. 15 shows the circuit configuration of the conventional charge pump 2, which comprises an output circuit 101 connected to a current source circuit 200. The current source circuit 200 includes a current source block 200a that feeds current IOUTa into the loop filter 3 to raise the control voltage VC output from the loop filter 3 to the voltage-controlled oscillator 4, and a current source block 200b that draws current IOUTb from the loop filter 3 to lower the control voltage VC.
FIG. 16 shows a circuit diagram of the analog-to-digital converter 8 and the current source circuit 200 in the conventional local oscillator circuit. The analog-to-digital converter 8 comprises comparators 801, 802, 803, resistors 804, 805, 806, 807, and an input terminal 808 receiving the control voltage VC. The current source circuit 200 includes current sources J1a, J1b, J2a, J2b, J3a, J3b, analog switches S1a, S1b, S2a, S2b, S3a, S3b, a terminal 106a for feeding current IOUTa, and a terminal 106b for drawing current IOUTb. Analog switches S1a and S1b may be omitted, as in FIG. 15. (For further information, see J. Craninckx and M. Steyaert, CMOS Wireless Frequency Synthesizer Design, Kluwer Academic Publishers, 1998).
If K indicates the frequency sensitivity of the voltage-controlled oscillator 4 (measured in hertz per volt) IOUT indicates current output from the charge pump 2, and f indicates the programmed frequency setting, then the lock time (the length of time needed by the local oscillator circuit to bring the output frequency fout to the frequency setting f) is directly proportional to the reciprocal of the product K×IOUT of the frequency sensitivity K and current IOUT. If the output frequency fout is externally perturbed away from the frequency setting f, the recovery time (the time needed to restore fout to f) is also directly proportional to the reciprocal of the product K×IOUT.
FIGS. 17A and 17B illustrate operating characteristics of the conventional local oscillator circuit in FIG. 14: FIG. 17A shows how the output frequency fout varies with the control voltage VC in the voltage-controlled oscillator 4; FIG. 17B shows how the output current IOUT varies with the control voltage VC. As is clear from the curve in FIG. 17A, the voltage-controlled oscillator 4 varies its output frequency fout responsive to the control voltage VC, raising the output frequency fout as the control voltage VC rises, but the frequency sensitivity K, defined as the slope of the curve in FIG. 17A, also varies with the control voltage VC of the voltage-controlled oscillator 4: the higher the control voltage VC is (the higher the output frequency fout), the lower the frequency sensitivity K becomes.
If the current IOUT output from the charge pump 2 does not vary according to the output frequency fout, but has a constant value as illustrated by the dotted line B′ in FIG. 17B, then since the frequency sensitivity K varies with the control voltage VC and the output frequency fout, the lock time and recovery time vary according to the frequency setting f: the higher the frequency setting f, the longer the lock time and recovery time become. If the product K X IOUT of frequency sensitivity K and current IOUT does not vary with the control voltage VC, but has a constant value, then the lock time and recovery time do not vary according to the frequency setting f.
Accordingly, in the circuit diagram shown in FIG. 16, comparators 801, 802, and 803 detect the control voltage VC, and the current IOUT output from the charge pump 2 is adjusted according to the detected control voltage VC as illustrated by curve B in FIG. 17B, so that the lock time in the conventional local oscillator circuit in FIG. 14 does not vary according to the frequency setting f. Although three comparators are shown in FIG. 16, actual circuits generally have five or more comparators.
Since the plurality of comparators in the analog-to-digital converter 8 operate constant1y, they consume power constant1y, which is a disadvantage. Power is also consumed constant1y by the resistor ladder comprising resistors 804, 805, 806, 807.